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| PRELIMINARY KM68V257C Document Title 32Kx8 Bit High Speed Static RAM(3.3V Operating), Evolutionary Pin out. CMOS SRAM Revision History Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to final Data Sheet. 1. Delete Preliminary 2.1. Add 28-TSOP1 Package. 3.1. Delete DIP Package. 3.2. Delete 20ns part 3.3. Add Capacitive load of the test environment in A.C test load Draft Data Jun. 1st, 1994 Oct. 4th, 1994 Remark Preliminary Final Rev. 2.0 Rev. 3.0 Feb. 22th, 1996 Feb. 25th, 1998 Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 3.0 February 1998 PRELIMINARY KM68V257C 32K x 8 Bit High-Speed CMOS Static RAM (3.3V Operating) FEATURES * Fast Access Time 15, 17ns(Max.) * Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 0.1mA(Max.) Operating KM68V257C - 15 : 90mA(Max.) KM68V257C - 17 : 80mA(Max.) * Single 3.30.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention; L-ver. only * Standard Pin Configuration KM68V257CJ : 28-SOJ-300 KM68V257CTG : 28-TSOP1-0813, 4F CMOS SRAM GENERAL DESCRIPTION The KM68V257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68V257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68V257C is packaged in a 300mil 28-pin plastic SOJ or TSOP1 forward. PIN CONFIGURATION(Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 TSOP1 FUNCTIONAL BLOCK DIAGRAM A14 1 28 Vcc 27 WE 26 A13 25 A8 24 A9 23 A11 Clk Gen. A3 A4 A6 A7 A8 A12 A13 A14 A5 Pre-Charge-Circuit A12 2 A7 3 A6 4 Row Select A5 5 Memory Array 512 Rows 64x8 Columns A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 SOJ 22 OE 21 A10 20 CS 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4 I/O1~I/O8 Data Cont. CLK Gen. A0 I/O Circuit Column Select I/O2 12 I/O3 13 Vss 14 PIN FUNCTION A1 A2 A9 A10 A11 Pin Name CS WE OE A0 - A14 WE CS OE I/O1 ~ I/O8 VCC VSS Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground -2- Rev 3.0 February 1998 PRELIMINARY KM68V257C ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 4.6 -0.5 to 4.6 1.0 -65 to 150 0 to 70 Unit V V W C C CMOS SRAM * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.2 -0.3* Typ 3.3 0 Max 3.6 0 VCC+0.3** 0.8 Unit V V V V * VIL(Min) = -2.0(Pulse Width 12ns) for I 20mA ** VIH(Max) = VCC+2.0V(Pulse Width 12ns) for I 20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70C,VCC=3.30.3V, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA 15ns 17ns Min -2 -2 2.4 Max 2 2 90 80 30 0.1 0.4 mA mA V V Unit A A mA Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 7 Unit pF pF * Capacitance is sampled and not 100% tested. -3- Rev 3.0 February 1998 PRELIMINARY KM68V257C AC CHARACTERISTICS(TA=0 to 70C, VCC=3.30.3V, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Value 0V to 3V 3ns 1.5V See below CMOS SRAM Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V RL = 50 DOUT VL = 1.5V ZO = 50 30pF* 319 DOUT 353 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD KM68V257C-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 KM68V257C-17 Min 17 3 0 0 0 3 0 Max 17 17 8 8 8 17 Unit ns ns ns ns ns ns ns ns ns ns ns -4- Rev 3.0 February 1998 PRELIMINARY KM68V257C WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW KM68V257C-15 Min 15 11 0 11 11 15 0 0 8 0 0 Max 6 KM68V257C-17 Min 17 12 0 12 12 17 0 0 8 0 0 Max 6 Unit ns ns ns ns ns ns ns ns ns ns ns CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Valid Data tAA Valid Data -5- Rev 3.0 February 1998 PRELIMINARY KM68V257C TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) Valid Data tPU 50% tPD 50% tOH tOHZ tHZ(3,4,5) CMOS SRAM CS NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5) -6- Rev 3.0 February 1998 PRELIMINARY KM68V257C TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) CMOS SRAM tWR(5) tWP1(2) tDH TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5) High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -7- Rev 3.0 February 1998 PRELIMINARY KM68V257C FUNCTIONAL DESCRIPTION CS H L L L WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC CMOS SRAM * NOTE : X means Dont Care. DATA RETENTION CHARACTERISTICS(TA=0 to 70C) Parameter VCC for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time Symbol VDR IDR tSDR tRDR Test Condition CSVCC - 0.2V VCC = 3.0V, CSVCC - 0.2V See Data Retention Wave form(below) Min. 2.0 0 5 Typ. Max. 3.6 0.07 Unit V mA ns ms DATA RETENTION WAVE FORM CS controlled VCC 3.0V tSDR Data Retention Mode tRDR VIH VDR CSVCC - 0.2V CS GND -8- Rev 3.0 February 1998 PRELIMINARY KM68V257C PACKAGE DIMENSIONS 28-SOJ-300 #28 #15 CMOS SRAM Units:millimeters/Inches 7.62 0.300 8.51 0.12 0.335 0.005 6.86 0.25 0.270 0.010 0.20 #1 18.82 MAX 0.741 18.41 0.12 0.725 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 +0.10 -0.05 +0.10 -0.05 +0.10 -0.05 #14 0.69 MIN 0.027 0.008+0.004 -0.002 3.76 MAX 0.148 0.10 0.004MAX ( 0.95 ) 0.0375 0.43 0.017 +0.004 -0.002 1.27 0.050 0.71 0.028+0.004 -0.002 28-TSOP1-0813.4F Units:millimeters/Inches 0.10 MAX 0.004 MAX +0.10 -0.05 0.008 +0.004 -0.002 0.20 13.40 0.20 0.528 0.008 #28 ( 0.425 ) 0.017 #1 8.40 0.331 MAX 0.55 0.0217 #14 #15 0.25 0.010 TYP 11.80 0.10 0.465 0.004 1.00 0.10 0.039 0.004 0.15 0.006 +0.10 -0.05 +0.004 -0.002 8.00 0.315 1.20 0.047 MAX 0.05 0.002 MIN 0~8 0.50 ) 0.020 0.45 ~0.75 0.018 ~0.030 ( -9- Rev 3.0 February 1998 |
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